1 Gigahertz Single-Core Processor Louisville KY

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Originally published at Internet.com

PMC-Sierra has expanded the company's RM9000 family of highly integrated, MIPS-based processors with its new 1 GHz single-core RM9000x1. The RM9000x1 integrates memory and high-speed I/O interfaces on-chip to optimize performance (see figure 1) and uses a 0.13 micron low voltage process to reduce total device power consumption to an industry low of less than 5 watts. The RM9000x1 is ideal for use in core and edge routers, DSLAMS, multi-service switches, high-end laser printers, storage area network (SAN) applications, and wireless base stations. The RM9000x1's 64-bit MIPS-based CPU core is compatible with the MIPS-64 Instruction Set Architecture. The CPU is optimized for performance by using a seven-stage dual-issue pipeline combined with tightly coupled L1 and L2 caches and sophisticated branch prediction for maintaining pipeline efficiency. To reduce memory latency for packet header processing, the RM9000x1 provides the Direct Deposit Cache feature allowing the Direct Memory Access of packet headers into L2 cache from the HyperTransport or SysAD buses while the payload is written into main memory.

The integrated high-speed bus interfaces provide low latency accesses to main memory and high bandwidth for I/O. A 200 MHz integrated DDR SDRAM interface provides 25.6 Gbit/s of memory bandwidth. The 500 MHz DDR HyperTransport and 200 MHz 64-bit SysAD I/O interfaces provide high bandwidth connections to a wide range of networking peripherals. For example, the HyperTransport link enables the RM9000x1 to connect other processors and co-processors such as security processors or classifiers, as well as to high-speed, HyperTransport switches and bridges, backplanes, and FPGAs. The local bus provides connectivity to lower speed devices such as boot ROM and Flash. To guarantee that data movement does not slow packet processing, the RM9000x1 has an embedded switch fabric. This buffered fabric, the Packet Switch, connects the CPU, memory and I/O interfaces. The Packet Switch has five ports supporting an aggregate bandwidth of 160 Gbit/s. The high bandwidth Packet Switch improves overall performance by allowing simultaneous data transfers on all five of its ports. The Packet Switch, for example, will allow a CPU access over SysAD at the same time that a HyperTransport peripheral is accessing the main memory.

* Related URLs: PMC-Sierra