Achieving PCI Express physical-layer Boston MA

With the emergence of the PCI Express 2.0 specification, data-transfer rates doubled from 2.5 GT/s to 5.0 GT/s. To develop effective receiver and transmitter tests for this faster rate, you'll need an understanding of PCI Express specifications as well as knowledge of system architectures, receiver tolerance measurements, stress elements, and transmitter PLL response.

In the 1-hr Webcast ?Pass PCI Express physical layer compliance testing the first time,? Bent Hessen-Schmidt, VP of business development at SyntheSys Research, covers these topics and describes trends in jitter compliance methodology.

Schmidt cites evidence of the difficulties of migrating to PCI Express 2.0: During the first half of 2007, only 10% of 2.5-GT/s PLL designs failed, while 60% of 5-GT/s implementations did. He notes that it is important that both the transmitter and receiver in a common-clock PCI Express design should track the single reference clock nearly identically to prevent clock jitter from contaminating data. He describes using a spectrum analyzer and a clock PLL analyzer to characterize PLL, contending that the clock analyzer provides better accuracy and repeatability.

Schmidt ends by describing dual-port measurements and saying that test methods are evolving to favor the use of sampling instruments as PCI Express speeds move toward 8-GT/s, with the concomitant 20-GHz fifth-order harmonics.