provided by: EDNActel has extended its Igloo series of low-power FPGAs with Igloo Plus. Whereas the company designed the original devices for maximum density, it optimized the new parts for I/O count. The core-logic structures remain the same as in the earlier parts. The three-device family spans 30,000 to 125,000 gates with 120, 157, or 212 I/Os. They have as much as 64% more I/Os per equivalent device than the earlier parts, arranged in four banks.
You can hot-swap the connections, which have Schmitt-trigger inputs for noise tolerance. As with the Igloo series, they support Actel?s Flash Freeze feature, which allows you to place the device in a very-low-power standby mode that nevertheless holds I/O states and from which the device can wake in 1 µsec.
Actel envisages that designers will use the chips for functions such as level shifting, general-purpose-I/O expansion, address- and data-bus multiplexing and decoding, interface translations, and general glue logic. The 30,000-system-gate part has a static power consumption of 5 µW. Allowing for the I/O orientation of the Plus series, this consumption is as much as 16 times lower power per I/O than that of some competitive devices, the company asserts. The latest release of Actel?s Libero-design package includes a pushbutton power-optimization option, which you use as a postdesign step to reduce power usage. It will have a minimal effect on performance, impacting speed by a few percentage points at most. Moreover, the tool gives you feedback on which areas of the design use the most power; a cycle-accurate analysis looks at peak power per cycle as well as average power over the entire simulation. You can also translate this information into a battery-life prediction. Igloo Plus chips will cost slightly less than $2 to $4 (250,000).
Actel, www.actel.com.
author: by Graham Prophet
EDN. Copyright © 2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.