provided by: EDNA delta-sigma converter uses many samples from the modulator to produce a stream of 1-bit codes. The delta-sigma ADC accomplishes this task by using an input-signal quantizer running at a high sample rate. Like all quantizers, the delta-sigma modulator takes an input and produces a stream of digital values that represents the voltage of the input. You can look at the delta-sigma modulator in the time or in the frequency domain. If you look at a time-domain representation, you can see the mechanics of a first-order modulator (Figure 1).
The modulator measures the difference between the analog-input signal and the analog output of a feedback DAC. An integrator then measures the analog-voltage output of the summing junction and presents a sloping signal to the 1-bit ADC. The 1-bit ADC converts the integrator?s output signal to a digital one or zero. Using the system clock, the ADC sends the 1-bit digital signal to the modulator?s output, as well as back through the feedback loop, where a 1-bit DAC is waiting.
The 1-bit ADC digitizes the signal to a coarse output code that has the quantization noise (ei) of the converter. The modulator output is equal to the input plus the quantization noise, (ei?ei?1). As this formula shows, the quantization noise is the difference of the current error (ei) minus the previous error (ei?1) of the modulator. The time-domain output signal is a pulse-wave representation of the input signal at the sampling frequency, fS. If you average the output-pulse train, it equals the value of the input signal.
The frequency-domain diagram tells a different story (Figure 2). The time-domain output pulses in the frequency domain appear as the input signal (or spur) and shaped noise. The noise characteristic in Figure 2 is the key to the modulator?s frequency operation.
Unlike most quantizers, the delta-sigma modulator includes an integrator that shapes the quantization noise. The noise spectrum at the modulator output is not flat. More important, in a frequency analysis, you can see how the modulator shapes the noise to higher frequencies, facilitating the production of a higher resolution result.
The modulator output in Figure 2 shows that the quantization noise of the modulator starts low at 0 Hz, rises rapidly, and then levels off at a maximum value at the modulator sampling frequency.
Integrating twice with a second-order modulator, instead of just once, is a great way to minimize low-frequency quantization noise. Most delta-sigma modulators are of a higher order. For instance, the designs of the more popular delta-sigma converters include second-, third-, fourth-, fifth, or sixth-order modulators. Multi-order modulators shape the quantization noise even harder to higher frequencies.
Bonnie Baker is a senior applications engineer at Texas Instruments. You can reach her at bonnie@ti.com.
References:References
- Baker, Bonnie, ?Delta-sigma ADCs in a nutshell,? EDN, Dec 14, 2007, pg 22, www.edn.com/article/CA6512148.
- Baker, RJ, CMOS mixed-signal circuit design, Wiley & Sons, ISBN 0471227544, May 2002.
author: by Bonnie Baker
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