Etch Faces New Challenges at 45 and 32 nm Washington DC

Success in semiconductor etch processes is measured by control - control of the etch profile (the shape of the hole or trench being created); control of damage and residue; and control of critical dimensions (CDs), including line edge roughness (LER) and linewidth roughness (LWR). Also of concern is cost of ownership, which is impacted by parameters such as etch rate (which determines overall throughput), the time between cleans (etch byproducts build up on chamber walls and must be regularly removed through a remote plasma clean) and the cost of consumables. Another major concern is control of uniformity and variability: across-the-wafer, wafer-to-wafer, batch-to-batch and tool-to-tool. One of the biggest contributors to non-uniformity is microloading, caused by different etch rates for densely packed features vs. open or isolated features.

None of this is new - it's just getting more difficult. One obvious challenge is that smaller features must be created as the industry heads to the 45 and 32 nm device generations. This requires new lithographic approaches, including thinner resist layers, which, in turn, is driving increased use of hard masks and more complex processes, such as bilayer resists. It may also necessitate the use of mask "trimming," where an etch process is used to create a narrower opening than can otherwise be achieved. The industry is also employing a wider range of new materials, including high-k gate dielectrics and proprietary gate metals with fine-tuned work functions. These new materials, particularly the metals, can create etch byproducts that are difficult to volatize and chamber residue that is difficult to remove. In the interconnect area, where dual-damascene patterning is done by etching holes and vias in low-k dielectrics, the challenge lies in managing the impact of using various types of etch stops and hard masks and different process flows (i.e., via-first vs. trench-first) on factors such as damage, variability and effective k (keff)value. Etch engineers are also faced with an increasingly complex stack of materials - eight or more in advanced devices - including photoresist, hard masks, antireflective coatings (ARCs), capping layers and etch-stop layers. And in there somewhere is the material actually being etched, such as a porous low-k dielectric.

Akio Yamamoto, chief engineer, applications technology department, Hitachi High-Technologies' (Berkshire, UK) semiconductor equipment business group, said the primary etch challenges for the 45 and 32 nm generations are high-k/metal gate for silicon, porous low-k for dielectric, and hard mask aluminum etching. "Also, double-patterning lithography on these materials is very challenging," he said.

Another new and unique etch challenge is presented by 3-D integration, where holes must be etched completely through a thinned silicon wafer. These deep through-silicon via (TSV) etches require specialized processes, so much so that it is one of the main focal points of a new consortium, ECM-3D (see "EMC-3D Consortium Targets Cost-Effective TSV Interconnects," p. SP-7).

Etch process basics

Both wet and dry etch processes are used throughout the semiconductor industry, depending on the application. The main advantages of wet processes are that they are relatively inexpensive and offer high selectivity (measured as the etch rate of one material vs. another, typically the photoresist mask and the material being etched). However, since it is difficult to provide much directionality to the etch, the resulting profile is typically isotropic. Of course, that's desirable in some cases, and in other cases the material is entirely removed from the wafer so it is not an issue. But for applications that require an anisotropic etch (i.e., the sidewalls are vertical) or a more tailored profile, a dry etch is the best choice (Fig. 1).

At the heart of a dry etch system is a plasma, which is a contained area of high-energy electric and magnetic fields that will rapidly dissociate gases present to form energetic ions, photons, electrons and highly reactive chemical species. The efficiency or "strength" of a plasma is evaluated by measuring parameters, such as electron temperature (eV), plasma density (ions/cm³), ion current density (mA/cm³) and ion energy. Etching action occurs by drawing energetic ions and reactive species out of the plasma and directing them at the wafer. Typically, a chlorine-based chemistry is used for etching polysilicon, silicides and metals, where fluorine-based chemistry is used for oxide and nitride etching. Improvements in selectivity and etch rate are obtained with the addition of argon, hydrogen, nitrogen and/or oxygen.

Some of the variables in an etch system include the size and shape of the chamber, the way in which the power (typically RF) is delivered into the plasma, how the plasma is confined, how the wafer is biased, and the distance between the wafer and plasma. Plasma engineers tend to talk about "knobs" that they can use to control the plasma. One of the most critical capabilities is to have separate control of ions and "neutrals" in the plasma. The design of the chuck that holds the wafer is also critical, particularly when it comes to etching materials such as metals, which are more volatile at higher temperatures. New chucks built with ceramics can operate at higher temperatures.

Another important aspect of etch is the option of using sidewall passivation. Here, carbon from the photoresist and source gas reacts with etch byproducts to form a polymer-like material on the sidewalls of the features. This has the benefit of helping to block etching of the sidewall, leading to increased anisotropy. The disadvantage is that it can be difficult to remove the etch after strip. If it's not removed, it acts as a source of contamination or "poisoning."

Specific goals depend on the material being etched, the material on which the etch stops, the amount of overetch required, sensitivity to damage, etc. Process optimization is usually about managing trade-offs. For example, the use of a higher power at a lower pressure will result in better residue control because of a higher ion density, but a higher-pressure process with relatively low plasma density provides better etch rate microloading control, higher selectivity and a higher etch rate. "It is important to select the right chemistry and optimize the process conditions - plasma density/DC bias and mean free path," noted Koichi Yatsuda of Tokyo Electron Ltd. (Tokyo). "The smaller the critical dimension, the narrower the process window becomes. It may be necessary to use multistep etching for the 32 nm generation to achieve the requirements."

Thinner resists

The evolution of lithography tools has resulted in thinner photoresist layers and, as a result, increased use of hard masks. "Resist thicknesses have continued to decrease, and this coupled with line edge roughness issues is making hard masks essential and hard mask etch a must for all critical etch layers," said Uday Mitra, CTO for the etch product group at Applied Materials (Santa Clara, Calif.). "In the good old days, i-line resist thickness used to be 10,000 Å, and photoresist-to-etch selectivity was over 4:1. With deep UV, the thickness dropped to 3000-5000 Å and selectivity went down to 3:1. With 193 nm, those thicknesses are less than 2000 Å and selectivity to PR is 2. With immersion, those resist thicknesses are less than 1000 Å, and hard masks are pretty much a must."

The reason why thinner resists are required has to do, in part, with aspect ratio. "In the past, we were able to have 4:1 or 3:1, but the maximum these days is about 2.5:1 or even 2:1," said Will Conley, distinguished member of the optical lithography group at Freescale Semiconductor (Crolles, France). "This aspect-ratio reduction is related to pattern collapse, which is more of a problem with ArF materials vs. KrF materials. We are also attempting to gain for process capability." The more demanding etch selectivity requirements are also a function of the resist type: The etch resistance of ArF photoresists can be 20-40% less than current KrF photoresist systems. "Our 32 nm program resist thickness plans for gate are <100 nm; metal/active is <150 nm. This gives you some idea of what we are facing. We are working to put together a spin-on hard mask integration process due to low film thickness," he said.

Metal hard masks

Hard masks for dual-damascene interconnect processing have primarily been dielectric films. "It has two main functions: to assist in patterning of the dual-damascene structure for subsequent metal fill, and as a highly selective CMP stop layer. In addition, this layer is called upon to prevent fast diffusion of acid or base moieties that could interact detrimentally with the traditional acid-catalyzed photoresist systems employed at 248 nm and 193 nm," as stated in the International Technology Roadmap for Semiconductors (ITRS).¹

More recently, with the introduction of porous low-k films, there's been interest in moving to metal hard masks, typically titanium- or tantalum-based versions. A metal hard mask provides the best protection against resist poisoning, and works well for the porous low-k. In practice, a layer of photoresist and an underlying ARC layer are underlain by a layer of metal. The first step is a hard mask open to etch the trench width through this metal layer, after which the wafer is ashed, exposing the remaining metal. Next, another ARC is deposited and patterned for via etch. This protects the partial trench while the via width is etched to partially open the barrier layer and the wafer is ashed again. An ARC is deposited once more and patterned for completing the trench etch. After the trench is etched, any ARC remaining in the bottom of the via is removed in the ashing step before the barrier layer (partially opened during the initial via etch) is completely opened to the copper-filled trench below.

The main challenge of etching a metal hard mask is that the byproducts are not very volatile. "Although the introduction of these masks has a lot of benefits from an integration perspective, from the productivity and process strip perspective, they can create a lot of issues. To manage that, we've had to come up with more creative chemistries on how to clean the chambers, and also the chambers have to have new materials," Mitra said.

Sitaram Arkalgud, director of the interconnect program at Sematech (Austin, Texas), noted that to avoid shorting between the lines or adding to the keff due to an oxidized byproduct of the hard mask layer, it is necessary to remove the metal hard mask during subsequent CMP steps. "A metal hard mask gives you very good etch selectivity, and if you use a titanium- or tantalum-based metal layer, then you can also polish it off during the CMP completely. If you can do that, then there's very minimal impact on the yield or keff." This, however, can create a CMP challenge, which has led to low-downforce CMP work. "You have to make sure you don't get dishing in the low-k dielectrics," he said.

Plasma-induced low-k damage is also a critical concern, mostly because removing the damage can change CDs. "During etch and/or ash processing, methyl groups are depleted, and the surface turns into porous silicon dioxide," Yatsuda said. "Since the material becomes more porous as the device generation advances, low-k thinning effects are enhanced in addition to scaling down CD. To correct it, etch and ash processes need to be optimized to generate minimum low-k damage. It may be necessary to restore the damaged low-k layer with a new unit process."

Etch stops

Another key part of dual-damascene patterning, which has an impact on etch requirements, is the trench etch-stop layer. The primary function of the trench etch stop is to provide adequate etch selectivity, as compared with the trench-level dielectric, to form a smooth well-defined trench bottom. Significant trench bottom roughness can be a reliability issue if it affects metal barrier coverage. Variability in trench depth can be a significant contributor to variation in metal line resistance. "If you have varying trench depth or if you have a rough trench bottom, then controlling the resistance of the line becomes more difficult," Arkalgud said. Fortunately, it is possible to eliminate the trench etch-stop layer to reduce keff. "The idea is just to get rid of that whole layer and have a stopless integration: No stop layer, but get a smooth trench bottom," Arkalgud said. "That also helps with the overall keff value because now you don't have a higher-k layer embedded in your low-k dielectic."

On the other hand, removing the trench etch-stop layer can lead to increased capacitance and metal variation (Fig. 2, p. 53). Speaking at last month's Industry Strategy Symposium, Hans Stork, CTO of Texas Instruments (Austin, Texas), made this observation: "Interconnect has become a bigger part of the overall performance. As you introduce variations that are undoubtedly going to be there because of deposition, planarization, etching and so forth, you can see that it has a very significant downside in the keff. This is clearly an area where variations have a very direct impact on the designer's ability to minimize margins."

The final piece of the interconnect etch puzzle is the via etch-stop layer, which has two main functions. It must have adequate etch selectivity with respect to the via dielectric layer so that etching of the underlying intermetal dielectric (IMD) adjacent to non-landed vias is avoided. It also serves as the cap for the underlying copper wiring layer. It must be a copper diffusion barrier and have acceptable adhesion and interface properties so that copper electromigration requirements are met. The via etch-stop layer can also be a significant contributor to overall keff, so its thickness and k value should both be minimized.

The Table (p. 53) shows several possible changes to this capping layer and the impact on keff. The largest gain in keff (11%) is obviously gained from omitting the cap entirely. Shifting to a lower-k material (i.e., a spin-on material at 2.8) reduces keff significantly more than thinning the cap (8.7 vs. 2.7%).

"We are looking at dropping the thickness [to reduce its k value], but the reliability is starting to become tougher to control," Arkalgud said. "Another knob that we tried to tweak is to drop the density of the layer, and that would bring down the k. But again it's a reliability issue that we ran into. They go hand in hand. On one hand, you need that good, hard etch stop, but at the same time, good electromigration control."