Processor For Nonintrusive Real-Time-Trace Block Philadelphia PA

All Tensilica configurable processor cores now support an optional nonintrusive real-time-trace block that includes the hardware and software necessary for tracing software-program execution. The Nexus 5001-compatible Trax-PC trace macrocell supports real-time implementation in silicon and in FPGAs. Software-debugging support includes visualization tools through Tensilica?s Xplorer. The trace block compresses the data from the trace port and buffers the compressed data in a user-supplied trace buffer, which users can access from outside the system through the JTAG TAP (test-access port). The Trax-PC can trace all changes in program flow, including exceptions and interrupts, and it can accept PC-based external-trigger inputs. The host software decompresses the trace data, reconstructs the program execution, and provides annotated program-disassembly and application-source listings through the Xplorer debugger.

Tool-enhancement features include automated generator support for the Xtensa LX2 FLIX (flexible-length-instruction-extension) instructions that manage profiling the application code and suggesting VLIW (very-long-instruction-word) instructions for accelerating the performance of that code. The generator automatically fuses two or three instructions that will execute simultaneously, without requiring the designer to understand how to write TIE (Tensilica-instruction-extension) code. Tool enhancements include a manual fusion editor that graphically assists designers in creating chains or fusions of operations to accelerate code execution. The cycle-accurate ISS (instruction-set simulator) has seen a 15 to 30% speed improvement, depending on whether the designer is using memory modeling. The new dynamic loader allows designers to load binaries in different memory addresses at runtime. The Xenergy energy-estimator tool now includes memory with the core in its energy estimates; it can graphically chart the energy profile for instruction- and data-cache configurations to provide a visual comparison of energy profiles.

The company also recently announced its smallest processor core, the Diamond Standard 106Micro core. The product comes in speed- or area-optimized configurations and can operate as fast as 400 MHz or consume as little as 0.13 mm2 of silicon in a 90-nm G process. The core uses a 16-entry main-register file instead of a 32- or 64-entry configuration, and it includes support for relocatable exception vectors. The core includes an option for a low-area, multicycle, pipelined, 32×32-multiplication multiplier and software emulation of multiplication instructions as well as an option for a low-area divider. In addition to the AHB (advanced-high-performance-bus)-lite bridge, the core supports an AMBA (advanced-microcontroller-bus-architecture) AXI (advanced-extensible-interface) bridge. These cores are available now for licensing.

Tensilica, www.tensilica.com.