Synopsys develops Eclypse tool Montana

With the goal of allowing design teams to adopt advanced low power techniques, boost productivity, reduce risk and deliver high quality silicon in order to meet or exceed power, area, speed and yield objectives, Mountain View, Calif.-based semiconductor design and manufacturing software company Synopsys Inc http://www.synopsys.com today announced its Eclypse low power suite that includes system-level, verification, implementation and signoff tools, intellectual property (IP), methodologies and services for low power chip development.

The Eclypse suite aligns Synopsys? low power technologies into a single workflow that addresses each phase of the design process, the company noted.

Advanced low power design techniques, such as MTCMOS power gating, multi-voltage, and dynamic voltage and frequency scaling, force a major shift in how engineers create and verify chips, which can reduce power consumption in deep submicron chips but have traditionally required ad-hoc, time-consuming, risk-prone, and manual verification and implementation approaches, Synopsys reminded.

Building on more than 10 years of low power design experience, Eclypse includes new, advanced low power technologies such as enhanced clock gating and low power clock-tree synthesis to allow designers to optimize their clock structures for low power while also achieving required skew and timing goals.

Also, advanced multi-threshold leakage optimization constrains the ratio of Vt, options utilized, and aims to allow optimal leakage power recovery independent of a design?s process corners, while enhanced automation for power switch insertion and optimization is aimed at power planning exploration and ?what-if? analysis using IR drop and area constraints, the company noted.

Eclypse supports the Unified Power Format (UPF) language, used to capture low power design requirements. The following UPF-enabled tools are included: MVRC and VCS with MVSIM, key components of the Discovery Verification Platform, and Design Compiler, Power Compiler, IC Compiler, DFT MAX, Formality, and PrimeTime, key components of the Galaxy Design Platform.

Completing the suite are additional tools for low power design, including Innovator, HSPICE, HSIM, NanoSim, TetraMAX, and PrimeRail, as well as DesignWare IP and Synopsys Professional Services. 

Eclypse also supports open methodologies, including those described in the ?Low Power Methodology Manual,? co-authored by Synopsys and ARM.

?The Eclypse low power solution is the result of an intensive, multi-year effort to create the industry?s most comprehensive and silicon-proven solution for low power chip development. With Eclypse, Synopsys has aligned its proven low power tools, IP, methodologies and services into an easy-to-use solution so that design teams can quickly and confidently adopt the most advanced low power techniques,? said George Zafiropoulos, VP of solutions marketing at Synopsys, in a statement.

Rounding out its offering, Synopsys will host a series of low power seminars http://www.synopsys.com/eclypse around the world to educate customers on Eclypse, with ARM participating. The seminars are designed to help chip development teams understand how they can employ the latest advanced low power design techniques with the Eclypse solution and will include an overview of the Eclypse solution and detail key elements of an automated low power design workflow.

Eclypse is available today, with pricing based on configuration.